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fn6979 rev 2.00 page 1 of 23 june 23, 2016 fn6979 rev 2.00 june 23, 2016 qlx4600-s30 quad lane extender datasheet the qlx4600-s30 is a settable quad receive-side equalizer with extended functionality fo r advanced protocols operating with line rates up to 6.25gb/s such as displayport v1.2 (hbr1/2), infiniband (sdr and ddr), pci express and 10gbase-cx4. the qlx4600-s30 compensates for the frequency dependent attenuation of copper twin-axial cables, extending the signal reach up to 30m on a 24awg cable. the small form factor, highly-integrated quad design is ideal for high-density data transmi ssion applications including active copper cable assemblies. the four equalizing filters within the qlx4600-s30 can each be set to one of 32 compensation levels, providing optimal signal fidelity for a given media and length. the compensation level for each filter can be set by either (a) three external control pins or (b) a serial bus interface. when the external control pins are used, 18 of the 32 boost levels are available for each channel. if the serial bus is used, all 32 compensation levels are available. operating on a single 1.2v power supply, the qlx4600-s30 enables per channel throughputs of up to 6.25gb/s while supporting lower data rates including 5, 4.25, 3.125 and 2.5gb/s. the qlx4600-s30 uses current mode logic (cml) inputs/outputs and is packaged in a 4mmx7mm 46 ld tqfn. individual channel power-down support is included for pci express applications. features ? supports data rates up to 6.25gb/s ? low power (78mw per channel) ? low latency (<500ps) ? four equalizers in a 4mmx7mm tqfn package for straight route-through architecture and simplified routing ? each equalizer boost is independently pin selectable and programmable ? beacon signal support and line silence preservation ? channel power-down for each equalizer ? 1.2v supply voltage applications ? displayport v1.2 active copper cable modules ? infiniband (sdr and ddr) ? 10gbase-cx4 ? pci express gen 1 and 2 ? xaui and rxaui, sas (1.0 and 2.0) ?high-speed active cable assemblies ? high-speed printed circuit board (pcb) traces benefits ?thinner gauge cable ? extends cable reach greater than 3x ?improved ber figure 1. typical application circuit
qlx4600-s30 fn6979 rev 2.00 page 2 of 23 june 23, 2016 ordering information part number ( notes 1 , 2 , 3 )part marking temp. range (c) tape and reel (units) package (rohs compliant) pkg. dwg. # QLX4600SIQT7 qlx4600siq 0 to +70 1k 46 ld tqfn l46.4x7 qlx4600siqsr qlx4600siq 0 to +70 100 46 ld tqfn l46.4x7 notes: 1. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ specia l pb-free material sets; molding compounds/die attach materials and nipdau plate - e4 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free products are msl classified at pb-free peak reflow temp eratures that meet or exceed the pb-fr ee requirements of ipc/jedec j std-020. 3. for moisture sensitivity level (msl), please see product information page for qlx4600-s30 . for more information on msl, please see tech brief tb363 . table 1. key differences between family of parts part number data rate (gb/s) number of tx or rx power consumption (mw) maximum cable length (24awg) (m) differential o/p swing (mv p-p ) de- emphasis (db) equalization (db) differences between qlx parts target market isl36411 11 4x rx 440 20 650 n/a 30 n/a dp1.3, 40gbe, qsfp+ isl35411 11 4x tx 340 20 600 4 n/a n/a dp1.3, 40gbe, qsfp+ qlx4600-sl30 6.25 4x rx 312 30 600 n/a 30 4 pins for loss of signal (los) dp1.2, sas-6gb, pcie 2.0 qlx4600-s30 6.25 4x rx 312 30 600 n/a 30 4 pins for impedance selection (= power down) dp1.2, sas-6gb, pcie 2.0
qlx4600-s30 fn6979 rev 2.00 page 3 of 23 june 23, 2016 pin configuration qlx4600-s30 (46 ld 4x7 tqfn) top view dt in1[p] in1[n] v dd in2[p] in2[n] v dd clk enb cp1[a] cp1[b] cp1[c] cp2[b] cp2[a] 1 2 3 4 5 6 7 46 45 44 43 42 41 40 8 9 10 11 12 13 14 15 39 16 17 18 19 20 21 22 23 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 in3[p] in3[n] v dd in4[p] in4[n] is1 is2 gnd bgref out1[p] out1[n] v dd out2[p] out2[n] v dd out3[p] out3[n] v dd out4[p] out4[n] is3 is4 mode cp2[c] exposed pad cp3[c] cp4[b] do cp3[a] di cp3[b] cp4[a] cp4[c] (gnd) pin descriptions pin name pin number description dt 1 detection threshold. reference dc current threshold for in put signal power detection. data output out[k] is muted when the power of the equalized version of in[k] falls below the threshold. tie to ground to disable electrical idle preservation and always enable the limiting amplifier. in1[p,n] 2, 3 equalizer 1 differential input, cml. the use of 100nf low esl/esr mlcc capacitor with at least 4ghz frequency response is recommended. v dd 4, 7, 10, 29, 32, 35 power supply. 1.2v supply voltage. the use of parallel 100pf and 10nf decoupling capacitors to ground is recommended for each of these pins for broa d high-frequency noise suppression. in2[p,n] 5, 6 equalizer 2 differential input, cml. the use of 100nf low esl/esr mlcc capacitor with at least 4ghz frequency response is recommended. in3[p,n] 8, 9 equalizer 3 differential input, cml. the use of 100nf low esl/esr mlcc capacitor with at least 4ghz frequency response is recommended. in4[p,n] 11, 12 equalizer 4 differential input, cml. the use of 100nf low esl/esr mlcc capacitor with at least 4ghz frequency response is recommended. is1 13 impedance select 1. cmos logic input. when the voltage on this pin is low, the single-ended input impedance of in1[p] and in1[n] each go above 200k and powers down the channel. this pin sh ould be connected to the fundamental reset signal in pci express?. otherwise, connect to v dd to hold the input impedance at 50 . is2 14 impedance select 2. cmos logic input. when the voltage on this pin is low, the single-ended input impedance of in2[p] and in2[n] each go above 200k and powers down the channel. this pin sh ould be connected to the fundamental reset signal in pci express?. otherwise, connect to v dd to hold the input impedance at 50 . gnd 15 ground
qlx4600-s30 fn6979 rev 2.00 page 4 of 23 june 23, 2016 di 16 serial data input, cmos logic. input for serial data stream to program internal registers controlling the boost for all fou r equalizers. synchronized with clock (clk) on pin 46. overrides the boost setting established on cp control pins. internally pulled down. do 17 serial data output, cmos logic. output of the internal re gisters controlling the boost for all four equalizers. synchronize d with clock on pin 46. equivalent to serial data input on di but delayed by 21 clock cycles. cp3[a,b,c] 18, 19, 20 control pins for setting equalizer 3. cmos lo gic inputs. pins are read as a 3-digit number to set the boost level. a is the msb, and c is the lsb. pins are internally pulled down through a 25k resistor. cp4[a,b,c] 21, 22, 23 control pins for setting equalizer 4. cmos lo gic inputs. pins are read as a 3-digit number to set the boost level. a is the msb, and c is the lsb. pins are internally pulled down through a 25k resistor. mode 24 boost-level control mode input, cmos logic. allows serial programming of internal registers through pins di, enb, and clk when set high. resets all internal registers to zero and uses boost levels set by cp pins when set low. if serial programming is not used, this pin should be grounded. is4 25 impedance select 4. cmos logic input. when the voltage on this pin is low, the single-ended input impedance of in4[p] and in4[n] each go above 200k and powers down the channel. this pin sh ould be connected to the fundamental reset signal in pci express?. otherwise, connect to v dd to hold the input impedance at 50 . is3 26 impedance select 3. cmos logic input. when the voltage on this pin is low, the single-ended input impedance of in3[p] and in3[n] each go above 200k and powers down the channel. this pin sh ould be connected to the fundamental reset signal in pci express?. otherwise, connect to v dd to hold the input impedance at 50 . out4[n,p] 27, 28 equalizer 4 differential output, cml. the use of 100nf low esl/esr mlcc capacitor with at least 4ghz frequency response is recommended. out3[n,p] 30, 31 equalizer 3 differential output, cml. the use of 100nf low esl/esr mlcc capacitor with at least 4ghz frequency response is recommended. out2[n,p] 33, 34 equalizer 2 differential output, cml. the use of 100nf low esl/esr mlcc capacitor with at least 4ghz frequency response is recommended. out1[n,p] 36, 37 equalizer 1 differential output, cml. the use of 100nf low esl/esr mlcc capacitor with at least 4ghz frequency response is recommended. bgref 38 external bandgap reference resistor. recommended value of 6.04k 1%. cp2[c,b,a] 39, 40, 41 control pins for setting equalizer 2. cmos lo gic inputs. pins are read as a 3-digit number to set the boost level. a is the msb, and c is the lsb. pins are internally pulled down through a 25k resistor. cp1[c,b,a] 42, 43, 44 control pins for setting equalizer 1. cmos logic inputs. pins are re ad as a 3-digit number to set the boost level. a is the msb, and c is the lsb. pins are internally pulled down through a 25k resistor. enb 45 serial data enable (active low), cmos logic. internal re gisters can be programmed with di and clk pins only when the enb pin is ?low?. internally pulled down. clk 46 serial data clock, cmos logic. synchronous clock for serial data on di and do pins. data on di is latched on the rising clock edge. clock speed is recommended to be between 10mhz and 20mhz. internally pulled down. exposed pad - exposed ground pad. for proper electrical and therma l performance, this pad should be connected to the pcb ground plane. pin descriptions (continued) pin name pin number description
qlx4600-s30 fn6979 rev 2.00 page 5 of 23 june 23, 2016 absolute maximum rating s thermal information supply voltage (v dd to gnd). . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 1.3v voltage at all input pins. . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to v dd + 0.3v esd rating at all pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2kv (hbm) thermal resistance (typical) ? ja (c/w) ? jc (c/w) 46 ld tqfn package (note 4) . . . . . . . . . . 32 2.3 operating ambient temperature range . . . . . . . . . . . . . . . . .0c to +70c storage ambient temperature range. . . . . . . . . . . . . . . . -55c to +150c maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . +125c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .see tb493 caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ? ja is measured with the component mounted on a high effective thermal conductivity test board in free air. see tech brief tb379 for details. 5. for ? jc , the ?case temp? location is the center of the exposed metal pad on the package underside. operating conditions parameter symbol test conditions min ( note 7 ) typ max ( note 7 )unit supply voltage v dd 1.1 1.2 1.3 v operating ambient temperature t a 0 2570c bit rate nrz data applied to any channel 1.5 6.25 gb/s control pin characteristics typical values are at v dd = 1.2v, t a = +25c, and v in = 800mv p-p , unless otherwise noted. v dd = 1.1v to 1.3v, t a = 0c to +70c. parameter symbol test conditions min ( note 7 ) typ max ( note 7 ) unit notes input ?low? logic level v il di, clk, enb 0 0 350 mv input ?high? logic level v ih di, clk, enb 750 v dd mv output ?low? logic level v ol is[k], do, mode 0 0 250 mv output ?high? logic level v oh is[k], do, mode 1000 v dd mv ?low? resistance state cp[k][a,b,c] 0 1 k 6 ?mid? resistance state cp[k][b,c] 22.5 25 27.5 k 6 ?high? resistance state cp[k][a,b,c] 500 k 6 input current current draw on digital pin, i.e., cp[k][a,b,c], di, clk, enb or mode 30 100 a note: 6. if four cp pins are tied together, the resistance values in this table should be divided by four.
qlx4600-s30 fn6979 rev 2.00 page 6 of 23 june 23, 2016 electrical specifications typical values are at v dd = 1.2v, t a = +25c, and v in = 800mv p-p , unless otherwise noted. v dd = 1.1v to 1.3v, t a = 0c to +70c. parameters symbol test conditions min ( note 7 )typ max ( note 7 )unit notes supply current i dd 260 ma cable input amplitude range v in measured differentially at data source before encountering channel loss 800 1200 1600 mv p-p 8 dc differential input resistance measured on input channel in[k] 80 100 120 dc single-ended input resistance measured on input channel in[k]p or in[k]n 40 50 60 input return loss (differential) s dd 11 50mhz to 3.75ghz 10 db 9 input return loss (common-mode) s cc 11 50mhz to 3.75ghz 6 db 9 input return loss (common-mode to differential conversion) s dc 11 50mhz to 3.75ghz 20 db 9 output amplitude range v out active data transmission mode; measured differentially at out[k]p and out[k]n with 50 load on both output pins 450 550 650 mv p-p line silence mode; measured differentially at out[k]p and out[k]n with 50 load on both output pins 10 20 mv p-p differential output impedance measured on out[k] 80 105 120 output return loss (differential) s dd 22 50mhz to 3.75ghz 10 db 9 output return loss (common-mode) s cc 22 50mhz to 3.75ghz 5 db 9 output return loss (common-mode to differential conversion) s dc 22 50mhz to 3.75ghz 20 db 9 output residual jitter 2.5gb/s, 3.1 25gb/s, 4.25gb/s, 5gb/s; up to 20m 24awg standard twin-axial cable (approximately -25db at 2.5ghz); 800mv p-p ? v in 1600mv p-p 0.15 0.25 ui 8 , 10 , 11 2.5gb/s, 3.125gb/s, 4.25gb/s, 5gb/s; 12m 30awg standard twin-axial cable (approximately -30db at 2.5ghz); 800mv p-p ? v in 1600mv p-p 0.20 0.30 ui 8 , 10 , 11 2.5gb/s, 3.125gb/s, 4.25gb/s, 5gb/s; 20m 28awg standard twin-axial cable (approximately -35db at 2.5ghz); 1200mv p-p ? v in 1600mv p-p 0.25 0.35 ui 8 , 10 , 11 6.25gb/s, up to 15m 28awg standard twin-axial cable (approximately -30db at 3.2ghz); 1200mv p-p v in 1600mv p-p 0.25 0.35 ui 8 , 10 , 11 output transition time t r , t f 20% to 80% 30 60 80 ps 12 lane-to-lane skew 50 ps propagation delay from in[k] to out[k] 500 ps los assert time time to assert loss-of-signal (los) indicator when transitioning from active data mode to line silence mode 100 s 13
qlx4600-s30 fn6979 rev 2.00 page 7 of 23 june 23, 2016 los deassert time time to assert loss-of-signal (los) indicator when transitioning from line silence mode to active data mode 100 s 13 data-to-line silence response time t ds time to transition from active data to line silence (muted output) on 20m 24awg standard twin-axial cable at 5gb/s 15 ns 13 , 16 time from last bit of align(0) for sas oob signaling to line silence (<20mv p-p output); meritec 24awg 20m; 3gb/s 14 ns 17 line silence-to-data response time t sd time to transition from line silence mode (muted output) to active data on 20m 24awg standard twin-axial cable at 5gb/s 20 ns 13 , 16 time from first bit of align(0) for sas oob signaling to 450mv p-p output; meritec 24awg 20m; 3gb/s 19 ns 17 timing difference (sas) |t ds - t sd | for sas oob signaling support; meritec 24awg 20m 5ns 17 notes: 7. compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 8. after channel loss, differential amplitudes at qlx4600-s 30 inputs must meet the input voltage range specified in ? absolute maximum ratings ? on page 5 . 9. temperature = +25c, v dd = 1.2v. 10. output residual jitter is the difference between the total ji tter at the lane extender output and the total jitter of the tr ansmitted signal (as measured at the input to the channel). total jitter (t j ) is dj p-p + 14.1 x rj rms . 11. measured using a prbs (2 7 -1) pattern. deterministic jitter at the input to the lane exte nder is due to frequency-dependent, media-induced loss only. 12. rise and fall times measured using a 1ghz clock with a 20ps edge rate. 13. for active data mode, ca ble input amplitude is 400mv p-p (differential) or greater. for line silence mode, cable input amplitude is 20mv p-p (differential) or less. 14. measured differentially across the data source. 15. during line silence, transmitter noise in excess of this voltage range may result in differential output amplitudes from the qlx4600 that are greater than 20mv p-p . 16. the data pattern preceding line silence mode is comprised of the pcie electrical idle ordered set (eios). the data pattern f ollowing line silence mode is comprised of the pcie electrical idle exit sequence (eies). 17. the data pattern preceding or following line silence mode is comprised of the sas-2 align (0) sequence for oob signaling at 3gb/s, and amplitude of 800mv p-p . electrical specifications typical values are at v dd = 1.2v, t a = +25c, and v in = 800mv p-p , unless otherwise noted. v dd = 1.1v to 1.3v, t a = 0c to +70c. (continued) parameters symbol test conditions min ( note 7 )typ max ( note 7 )unit notes serial bus timing characteristics parameter symbol condition min typ max unit clk set-up time t sck from the falling edge of enb 10 ns di set-up time t sdi prior to the rising edge of clk 10 ns di hold time t hdi from the rising edge of clk 6 ns enb ?high? t hen from the falling edge of the last data bit?s clk 10 ns boost setting operational t d from enb ?high? 10 ns do hold time t cq from the rising edge of clk to do transition 12 ns clock rate f clk reference clock for serial bus eq programming 20 mhz
qlx4600-s30 fn6979 rev 2.00 page 8 of 23 june 23, 2016 typical performance characteristics v dd = 1.2v, t a = +25c, unless otherwise noted. performance was characterized using the system testbed shown in figure 2 . unless otherwise noted, the transmitter generated a non-return-to-zero (nrz) prbs-7 sequence at 800mv p-p (differential) with 10ps of peak-to-peak deterministic jitter. this transmit signal was launched into twin-axial cable test channels of varying gauges and lengths. the loss characteristics of the se test channels are plotted as a function of frequency in figure 3 . the received signal at the output of these test chan nels was then processed by the qlx4600-s30 before being passed to a receiver. eye diagram measurements were made with 4000 waveform acquisitions and include random jitter. figure 2. device characterization test setup figure 3. twin-axial cable loss as a functi on of frequency for various test channels figure 4a. jitter vs cable length, 5gb/s figure 4b. jitter vs boost setting, 5gb/s figure 4. jitter vs cable length an d jitter vs boost setting at 5gb/s test channel loss characteristics 0 0.1 0.2 0.3 0.4 0.5 4 8 12 16 20 24 28 boost setting jitter (ui) cable a (24awg 20m) cable b (30awg 12m) cable c (28awg 20m)
qlx4600-s30 fn6979 rev 2.00 page 9 of 23 june 23, 2016 figure 5. received signal after 20m of 24awg twin-axial cable (cable a), 5gb/s figure 6. qlx4600-s30 output after 20m of 24awg twin-axial cable (cable a), 5gb/s figure 7. received signal after 12m of 30awg twin-axial cable (cable b), 5gb/s figure 8. qlx4600-s30 output after 12m of 30awg twin-axial cable (cable b), 5gb/s figure 9. received signal af ter 20m of 28awg twin-axial cable (cable c) ( note 18 ), 5gb/s figure 10. qlx4600-s30 output after 20m of 28awg twin-axial cable (cable c) ( note 18 ), 5gb/s typical performance characteristics (continued) 40ps/div 60mv/div 40ps/div 80mv/div 40ps/div 60mv/div 40ps/div 80mv/div 40ps/div 70mv/div 40ps/div 80mv/div
qlx4600-s30 fn6979 rev 2.00 page 10 of 23 june 23, 2016 figure 11. received signal after 30m of 24awg twin-axial cable ( note 18 ), 5gb/s figure 12. qlx4600-s30 output after 30m of 24awg twin-axial cable ( note 18 ), 5gb/s figure 13. received signal after 15m of 28awg twin-axial cable (cable d) ( note 18 ), 6.25gb/s figure 14. qlx4600-s30 output after 15m of 28awg twin-axial cable (cable d) ( note 18 ), 6.25gb/s figure 15. received signal after 40" fr4, 6.25gb/s figure 16. qlx4600-s30 output after 40" fr4, 6.25gb/s typical performance characteristics (continued) 40ps/div 70mv/div 40ps/div 80mv/div 32ps/div 70mv/div 32ps/div 80mv/div 32ps/div 70mv/div 32ps/div 80mv/div
qlx4600-s30 fn6979 rev 2.00 page 11 of 23 june 23, 2016 figure 17. input common-mode return loss figure 18. output comm on-mode return loss figure 19. input differential return loss figure 20. output differential return loss figure 21. differential crosstalk between adjacent input channel figure 22. differential crosstalk between adjacent input channels note: 18. differential transmit amplitude = 1200mv p-p. typical performance characteristics (continued) -30 -25 -20 -15 -10 -5 0 00.511.522.533.54 frequency (ghz) scc11 (db) channel 1 channel 2 channel 3 channel 4 -30 -25 -20 -15 -10 -5 0 0 0.5 1 1.5 2 2.5 3 3.5 4 frequency (ghz) scc22 (db) channel 1 channel 2 channel 3 channel 4 -35 -30 -25 -20 -15 -10 -5 0 00.511.522.533.54 frequency (ghz) sdd11 (db) channel 1 channel 2 channel 3 channel 4 -35 -30 -25 -20 -15 -10 -5 0 00.511.522.533.54 frequency (ghz) sdd22 (db) channel 1 channel 2 channel 3 channel 4
qlx4600-s30 fn6979 rev 2.00 page 12 of 23 june 23, 2016 operation the qlx4600-s30 is an advanced quad lane-extender for high-speed interconnect s. a functional diagram of one of the four channels in the qlx4600-s30 is shown in figure 23 . in addition to a robust equalization filter to compensate for channel loss and restore signal fidelity, the qlx4600-s30 contains unique integrated features to preserve special signaling protocols typically broken by other equalizers. the signal detect function is used to mute the channel output when the equalized signal falls below the level determined by the detection threshold (dt) pin voltage. this function is intend ed to preserve periods of line silence (?quiescent state? in infiniband contexts). as illustrated in figure 23 , the core of each high-speed signal path in the qlx4600-s30 is a so phisticated equalizer followed by a limiting amplifier. the equalizer compensates for skin loss, dielectric loss, and impeda nce discontinuities in the transmission channel. each equalizer is followed by a limiting amplification stage that provides a clean output signal with full amplitude swing and fast rise-f all times for reliable signal decoding in a subsequent receiver. individually adjustable equalization boost each channel in the qlx4600-s30 features an independently settable equalizer for custom sign al restoration. each equalizer can be set to one of 32 levels of compensation when the serial bus is used to program the boost level and one of 18 compensation levels when the cp[k] pins are used to set the level. the equalizer transfer functions for a subset of these compensation levels are plotted in figure 24 . the flexibility of this adjustable compensation architecture enables signal fidelity to be optimized on a channel-by-channel basis, providing support for a wide variety of channel characteristics and data rates ranging from 2.5 to 6.25 gb/s. because the boost level is externally set rather than internally adapted, the qlx4600-s30 provides reliable communication from the very first bit transmitted. there is no time ne eded for adaptation and control loop convergence. furthermore, there are no pathological data patterns that will cause the qlx4600-s30 to move to an incorrect boost level. ? applications information ? on page 13 details how to set the boost level by both the cp-pin voltage approach and the serial programming approach. cml input and output buffers the input and output buffers for th e high-speed data channels in the qlx4600-s30 are implemented using cml. equivalent input and output circuits are shown in figures 25 and 26 , respectively. adjustable equalizer signal detector - + detection threshold los[k] out[k] [p,n] limiting amplifier in[k] [p,n] eq setting (cp[k] / di) figure 23. functional diagram of a single channel within the qlx4600-s30 figure 24. equalizer transfer functions for settings 0, 5, 10, 15, 20, 25, and 31 in the qlx4600-s30
qlx4600-s30 fn6979 rev 2.00 page 13 of 23 june 23, 2016 line silence/electrical idle/quiescent mode line silence is commonly broken by the limiting amplification in other equalizers. this disruption can be detrimental in many systems that rely on line silenc e as part of the protocol. the qlx4600-s30 contains special lane management capabilities to detect and preserve periods of line silence while still providing the fidelity-enhancing benefits of limiting amplification during active data transmission. line silence is detected by measuring the amplitude of the equalized sign al and comparing that to a threshold set by the current at the dt pin. when the amplitude falls below the threshold, the outp ut driver stages are muted and held at their nominal common-mode voltage. note: the output common-mode voltage remains constant during both active data transmission and output muting modes. input impedance select the input impedance of a channel on the qlx4600-s30 is set high (>200k) when powered down or when the is[k] pin is pulled low. this provides compatibili ty with the fundamental reset signal and receiver detection/link initialization in the pci express protocol. channel power-down in addition to controlling the input impedance, the is[k] pin powers down the equalizer channel when pulled low. this feature allows a system controller indi vidually to power down unused channels and to minimize power consumption. example: the signal to power down a channel could come from an intelligent platform management controller in atca applications for e-keying. the current draw for a channel is reduced from 50ma to 3.8ma when powered down. applications information several aspects of the qlx4600-s30 are capable of being dynamically managed by a system controller to provide maximum flexibility and optimum performance. these functions are controlled by interfacing to the highlighted pins in figure 27 . the specific procedures for co ntrolling these aspects of the qlx4600-s30 are the focus of this section. equalization boost level channel equalization for the qlx4600-s30 can be individually set to either (a) one of 18 leve ls through the dc voltages on external control pins or (b) one of 32 levels via a set of registers programmed by a low speed serial bus. the pins used to control the boost level are highlighted in figure 27 . descriptions of these pins are listed in table 2 on page 14 . please refer to ? pin descriptions ? on page 3 for descriptions of all other pins on the qlx4600-s30. figure 25. cml input equi valent circuit for the qlx4600-s30 figure 26. cml output equivalent circuit for the qlx4600-s30 note: the load value of 52 is used to internally match s dd 22 for a characteristic impedance of 50 . in[k] p in[k] n buffer v dd 50 50 v dd 52 52 out[k] p out[k] n figure 27. pin diagram highlighting pins used for dynamic control of the qlx4600-s30 44 40 41 42 43 1 32 10 9 8 7 6 5 4 3 2 38 24 25 26 27 28 29 30 31 23 20 19 18 17 16 11 12 33 14 13 34 45 39 46 22 21 35 36 15 37 in1[p] in1[n] in2[p] in2[n] in3[p] in3[n] in4[p] in4[n] out1[p] out1[n] out2[p] out2[n] out3[p] out3[n] out4[p] out4[n] dt cp3[a] cp3[b] cp3[c] cp4[a] cp4[b] cp4[c] cp1[a] cp1[b] cp1[c] cp2[a] cp2[b] cp2[c] qlx4600-s30 46 ld qfn 7mm x 4mm 0.4mm pitch exposed pad (gnd) gnd is1 is4 nc di do clk enb is2 is3 bgref v dd v dd v dd v dd v dd v dd
qlx4600-s30 fn6979 rev 2.00 page 14 of 23 june 23, 2016 the boost setting for equalizer ch annel k can be read as a three digit ternary number across cp[k][a,b,c]. the ternary value is established by the value of the resistor between v dd and the cp[k][a,b,c] pin. as a second option, the equalizer boost setting can be taken from a set of registers prog rammed through a serial bus interface (pins 16, 17, 45, and 46). using this interface, a set of registers is programmed to store the boost level. a total of 21 registers are used. registers 2 through 21 are parsed into four 5-bit words. each 5-bit word determines which of 32 boost levels to use for the corresponding equalizer. register 1 instructs the qlx4600-s30 to use registers 2 through 21 to set the boost level rather than the control pins cp[k][a,b,c]. both options have their relative advantages. the control pin option minimizes the need for ex ternal controllers as the boost level can be set in the board design resulting in a compact layout. the register option is more flexible for cases in which the optimum boost level will not be known and can be changed by a host bus adapter with a small number of pins. it is noted that the serial bus interface can also be daisy-chained among multiple qlx4600-s30 devices to affo rd a compact programmable solution even when a large number of data lines need to be equalized. upon power-up, the default value of all the registers (and register 1 in particular) is zero, and thus, the cp pins are used to set the boost level. this permits an alte rnate interpretation on setting the boost level. specifically, the cp pins define the default boost level until the registers are (if ever) programmed via the serial bus. table 2. descriptions of pins that can be used to set equalization boost level pin name pin number description di 16 serial data input, cmos logic. input for serial data stream to program internal registers controlling the boost for all fou r equalizers. synchronized with clock (clk) on pin 46. overrides the boost setting established on cp control pins. internally pulled down. do 17 serial data output, cmos logic. output of the internal re gisters controlling the boost for all four equalizers. synchronize d with clock on pin 46. equivalent to serial data input on di but delayed by 21 clock cycles. cp3[a,b,c] 18, 19, 20 control pins for setting equalizer 3. cmos lo gic inputs. pins are read as a 3-digit number to set the boost level. a is the msb, and c is the lsb. pins are in ternally pulled down through a 25k resistor. cp4[a,b,c] 21, 22, 23 control pins for setting equalizer 4. cmos lo gic inputs. pins are read as a 3-digit number to set the boost level. a is the msb, and c is the lsb. pins are in ternally pulled down through a 25k resistor. mode 24 boost-level control mode input, cmos logic. allows serial programming of internal registers through pins di, enb and clk when set high. resets all internal registers to zero and uses boost levels set by cp pins when set low. if serial programming is not used, this pin should be grounded. cp2[c,b,a] 39, 40, 41 control pins for setting equalizer 2. cmos lo gic inputs. pins are read as a 3-digit number to set the boost level. a is the msb, and c is the lsb. pins are in ternally pulled down through a 25k resistor. cp1[c,b,a] 42, 43, 44 control pins for setting equalizer 1. cmos lo gic inputs. pins are read as a 3-digit number to set the boost level. a is the msb, and c is the lsb. pins are in ternally pulled down through a 25k resistor. enb 45 serial data enable (active low), cmos logic. internal regi sters can be programmed with di and clk pins only when the enb pin is ?low?. internally pulled down. clk 46 serial data clock, cmos logic. synchron ous clock for serial data on di and do pins . data on di is latched on the rising cl ock edge. clock speed is recommended to be between 10mhz and 20mhz. internally pulled down. table 3. mapping between cp-setting resistor and programmed boost levels resistance betwee n cp pin and v dd serial boost level cp[a] cp[b] cp[c] open open open 0 open open 25k 2 open open 0 4 open 25k open 6 open 25k 25k 8 open 25k 0 10 open 0 open 12 open 0 25k 14 open 0 0 15 0 open open 16 0 open 25k 17 0 open 0 19 0 25k open 21 0 25k 25k 23 0 25k 0 24 0 0 open 26 0 0 25k 28 0 0 0 31
qlx4600-s30 fn6979 rev 2.00 page 15 of 23 june 23, 2016 control pin boost setting when register 1 of the qlx4600-s30 is zero (the default state on power-up), the voltages at the cp pins are used to determine the boost level of each channel. for each of the four channels, k, the [a], [b], and [c] control pins (cp[k]) are associated with a 3-bit non binary word. while [a] can take one of two values, ?low? or ?high?, [b] and [c] can take one of three different values: ?low?, ?middle?, or ?high?. this is achi eved by changing the value of a resistor connected between the vdd and cp pins, which is internally pulled low with a 25k resistor. thus, a ?high? state is achieved by using a 0 resistor, ?middle? is achieved with a 25k resistor, and ?low? is achieved with an open resistance. table 3 on page 14 defines the mapping from the 3-bit cp word to the 18 out of 32 possible levels available via the serial interface. if all four channels are to use the same boost level, then a minimum number of board resistors can be realized by tying together like the cp[k][a,b,c] pins across all channels. for instance, all four cp[k][a] pins ca n be tied to the same resistor running to vdd. consequently, only three resistors are needed to control the boost of all four channels. if the cp pins are tied together and the 25k is used, the value changes to a 6.25k resistor because the 25k is divided by 4. optimal cable boost settings the settable equalizing filter within the qlx4600 enables the device to optimally compensate for frequency-dependent attenuation across a wide variety of channels, data rates and encoding schemes. for the reference channels plotted in figure 3 , table 4 shows the optimal boost setting when transmitting a prbs-7 signal. the optimal boost setting is defined as the equalizing filter setting that minimizes the output residual jitter of the qlx4600. the settings in table 4 represent the optimal settings for the qlx4600c across an ambient temperature range of 0c to +70c. the optimal setting at room temperature (+20c to +40c) is generally one to tw o settings lower than the values listed in table 5 on page 16 . register description the qlx4600-s30?s internal registers are listed in table 5 . register 1 determines whether the cp pins or register values 2 through 21 are used to set the boost level. when this register is set, the qlx4600-s30 uses registers 2-6, 7-11, 12-16, and 17-21 to set the boost level of equalizers 1, 2, 3, and 4. when register 1 is not set, the cp pins are used to determine the boost level for each equalizer channel. the use of five registers for each equalizer channel allows all 32 boost levels as candidate boost levels. table 4. optimal cable boost settings cable approx. loss at 2.5ghz (db) qlx4600-s30 boost cable a 22 10 cable b 27 14 cable c 35 19 note: optimal boost settings should be determined on an application-by-application basis to account for variations in channel type, loss characteristics and encoding schemes. the settings in table 4 are presented as guidelines to be used as a starting point for application-specific optimization.
qlx4600-s30 fn6979 rev 2.00 page 16 of 23 june 23, 2016 serial bus programming pins 16 (di), 45 (enb), and 46 (clk) are used to program the registers inside the qlx4600-s30. figure 28 on page 17 shows an exemplary timing diagram for the signals on these pins. the serial bus can be used to program a single qlx4600-s30 according to the following steps: 1. the enb pin is pulled ?low?. - while this pin is ?low?, the data input on di are read into registers but not yet latched. - a setup time of t sck is needed between enb going ?low? and the first rising clock edge. 2. at least 21 values are read from di on the rising edge of the clk signal. - if more than 21 values are passed in, then only the last 21 values are kept in a fifo fashion. - the data on di should start by sending the value destined for register 21 and finish by sending the value destined for register 1. - a range of clock frequencies can be used. a typical rate is 10mhz. the clock should not exceed 20mhz. -setup (t sdi ) and hold (t hdi ) times are needed around the rising clock edge. 3. the enb pin is pulled ?high? and the contents of the registers are latched and take effect. - after clocking in the last data bit, an additional t hen should elapse before pulling the enb signal ?high?. - after completing these steps, the new values will affect within t d . table 5. description of internal serial registers register equalizer channel description 1 1-4 cp control override ? use registers 2 through 21 (rather than cp pins) to establish the boost levels when this bit is set. 2 1 equalizer setting bit 0 (lsb). 3 equalizer setting bit 1. 4 equalizer setting bit 2. 5 equalizer setting bit 3. 6 equalizer setting bit 4 (msb). 7 2 equalizer setting bit 0 (lsb). 8 equalizer setting bit 1. 9 equalizer setting bit 2. 10 equalizer setting bit 3. 11 equalizer setting bit 4 (msb). 12 3 equalizer setting bit 0 (lsb). 13 equalizer setting bit 1. 14 equalizer setting bit 2. 15 equalizer setting bit 3. 16 equalizer setting bit 4 (msb). 17 4 equalizer setting bit 0 (lsb). 18 equalizer setting bit 1. 19 equalizer setting bit 2. 20 equalizer setting bit 3. 21 equalizer setting bit 4 (msb).
qlx4600-s30 fn6979 rev 2.00 page 17 of 23 june 23, 2016 programming multiple qlx4600-s30 devices the serial bus interface provides a simple means of setting the equalizer boost levels with a minimal amount of board circuitry. many of the serial interface si gnals can be shared among the qlx4600-s30 devices on a board and two options are presented in this section. the first uses common clock and serial data signals along with separate enb signals to select which qlx4600-s30 accepts the programmed changes. the second method uses a common enb signal as the serial data is carried-over from one qlx4600-s30 to the next. separate enb signals multiple qlx4600-s30 devices can be programmed from a common serial data stream as shown in figure 29 . here, each qlx4600-s30 is provided its own enb signal, and only one of these enb signals is pulled ?low?, and hence accepting the register data, at a time. in this situation, the programming of each equalizer follows the steps outlined in figure 30 on page 18 . di/do carryover the do pin (pin 17) can be used to daisy-chain the serial bus among multiple qlx4600-s30 chips. the do pin outputs the overflow data from the di pin. specifically, as data is pipelined into a qlx4600-s30, it proceeds according to the following flow. first, a bit goes into shadow register 1. then, with each clock cycle, it shifts over into subseq uent higher numbered registers. after shifting into register 21, it is output on the do pin on the same clock cycle. thus, the do signal is equal to the di signal, but delayed by 20 clock cycles. the timing diagram for the do pin is shown in figure 30 on page 18 where the first 20 bits output from the do are indefinite and su bsequent bits are the data fed into the di pin. the delay between the rising clock edge and the data transition is t cq . a diagram for programming multip le qlx4600-s30s is shown in figure 31 on page 18 . it is noted that the board layout should ensure that the additional cl ock delay experienced between subsequent qlx4600-s30s shou ld be no more than the minimum value of t cq , i.e., 12ns. r21 r20 r19 r1 t sdi t hdi t sck t hen di clk enb figure 28. timing diagram for programming the internal registers of the qlx4600-s30 qlx4600-s30 (a) enb clk di do qlx4600-s30 (b) enb clk di do qlx4600-s30 (c) enb clk di do qlx4600-s30 (d) enb clk di do enb (a) enb (b) enb (c) enb (d) clock serial register data figure 29. serial bus programming multiple ql x4600-s30 devices using separate enb signals
qlx4600-s30 fn6979 rev 2.00 page 18 of 23 june 23, 2016 figure 30. timing diagram for di/do carryover w 6&. '2 &/. (1% &orfn&\fohv w &4 vw 5lvlqj(gjh )luvw%lwiurp', 4/[6 $ (1% &/. ', '2 4/[6 % (1% &/. ', '2 4/[6 & (1% &/. ', '2 4/[6 ' (1% &/. ', '2 (1% &orfn 6huldo 5hjlvwhu 'dwd figure 31. serial bus programming multiple qlx4600-s30 devices using di/do carryover 5 5 5 w 6', w +', w 6&. w +(1 ', &/. (1% 5 5 5 5 5 5 4/[6' 4/[6& 4/[6% 4/[6$ figure 32. timing diagram for pr ogramming multiple qlx4600-s30 devices using di/do carryover
qlx4600-s30 fn6979 rev 2.00 page 19 of 23 june 23, 2016 detection threshold (dt) pin functionality the qlx4600-s30 is capable of maintaining periods of line silence on any of its four channels by monitoring each channel for loss of signal (los) conditio ns and subsequently muting the outputs of a respective channe l when such a condition is detected. a reference current applied to the detection threshold (dt) pin is used to set the los threshold of the internal signal detection circuitry. current control on the dt pin is done via one or two external resistors. nominally, both a pull-up and pull-down resistor are tied to the dt pin ( figure 33a ), but if adequate control of the supply voltage is ma intained to within 3% of 1.2v, then a simple pull-down resistor is adequate (as in figure 33b ). resistors used should be at least 1/16w, with 1% precision. the internal bias point of the dt pin, nominally 1.05v, is used in conjunction with the voltage divider (r 1 and r 2 ) shown in figure 33a to set the reference current on the dt pin. case 1: channels with less than or equal to 25db loss at 2.5ghz (1gb/s to 6gb/s): for signals transmitted on channels having less than or equal to 25db of loss at 2.5ghz, the optimal dt reference current is 0a. this optimal reference current may be achieved by either leaving the dt pin floating, or tying the dt pin to ground (gnd) with a 10m resistor. case 2: channels with greater than 25db loss at 2.5ghz (1gb/s to 6gb/s): for channels exhibiting more than 25db of total loss (this includes cable or fr-4 loss) the dt pin should be configured for a reference sink current (coming out of the dt pin) of approximately 2a. a typical configuration for a 2a sink current is given in figure 33c . if the configuration in figure 33b is utilized, a 525k resistor would be used. figure 33a. figure 33b. figure 33c. figure 33. dt 1.2v r 2 r 1 47nf gnd gnd dt gnd r 2 1.2v dt 42.2k 100k 47nf gnd gnd
qlx4600-s30 fn6979 rev 2.00 page 20 of 23 june 23, 2016 typical application reference designs figures 34 and 35 show reference design schematics for a qlx4600-s30 evaluation board with an sma connector interface. figure 34 shows the schematic for the case when the equalizer boost level is set via the cp pins. figure 35 shows the schematic for the case when the level is set via the serial bus interface. figure 34. application circuit for the qlx4600-s30 evaluation board using the control pins for setting the equalizer compensation level 1 2 3 4 5 6 7 8 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 16 17 18 19 20 21 22 23 9 10 11 12 13 14 15 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 di do cp3[a] cp3[b] cp3[c] cp4[a ] cp4[b] cp4[c] clk enb cp1[a] cp1[b] cp1[c] cp2[a] cp2[b] cp2[c] gnd is2 is1 mode is4 is3 1.2v 1.2v 1.2v 1.2v 1.2v 1.2v dt in1[p] in1[n] in2[p] in2[n] in3[p] in3[n] in4[p] in4[n] out2[p] out2[n] out4[p] out4[n] out1[p] out1[n] out3[p] out3[n] 6k bgref a qlx4600-s30 1.2v 100pf* 10nf bypass circuit for each v dd pin: 4, 7, 10, 29, 32, 35 (*100pf capacitor should be positioned closest to the pin ) eq boost control for channels 1 and 2 (see pages 15-17) nc nc nc nc detection threshold reference current qlx4600-s30 lane extender reference control pin mode quellan , inc. eq boost control for channels 3 and 4 (see pages 15-17) = sma connector a) dc blocking capacitors = x7r or cog 0.1f (>4ghz bandwidth) impedance select (channels 3 and 4) impedance select (channels 1 and 2) mode mode at 1.2v: serial control mode mode at gnd: binary control mode 1.2v 100k 47nf 42.2k
qlx4600-s30 fn6979 rev 2.00 page 21 of 23 june 23, 2016 about q:active? intersil has long realized that to enable the complex server clusters of next generation datacenters, it is critical to manage the signal integrity issues of elec trical interconnects. to address this, intersil has developed its groundbreaking q:active? product line. by integrating its analog ics inside cabling interconnects, intersil is able to achieve unsurpassed improvements in reach, power consumption, latency and cable gauge size as well as increased airflow in tomorrow?s datacenters. this new technology transforms passive cabling into intelligent ?roadways? that yiel d lower operating expenses and capital expenditures for the expanding datacenter. intersil lane extenders allow greater reach over existing cabling, while reducing the need for thicker cables. this significantly reduces cable weight and clutter, increases airflow and reduces power consumption. figure 35. application circuit for the qlx4600-s30 evaluation bo ard using the serial bus interface for setting the equalizer compensation level typical application reference designs (continued) figures 34 and 35 show reference design schematics for a qlx4600-s30 evaluation board with an sma connector interface. figure 34 shows the schematic for the case when the equalizer boost level is set via the cp pins. figure 35 shows the schematic for the case when the level is set via the serial bus interface. 1 2 3 4 5 6 7 8 46 45 44 43 42 41 40 39 16 17 18 19 20 21 22 23 9 10 11 12 13 14 15 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 gnd is2 is1 mode is4 is3 1.2v 1.2v 1.2v 1.2v 1.2v 1.2v dt in1[p] in1[n] in2[p] in2[n] in3[p] in3[n] in4[p] in4[n] out2[p] out2[n] out4[p] out4[n] out1[p] out1[n] out3[p] out3[n] 6k bgref a qlx4600-s30 1.2v 100pf* 10nf bypass circuit for each v dd pin: 4, 7, 10, 29, 32, 35 (*100pf capacitor should be positioned closest to the pin ) detection threshold reference current qlx4600-s30 lane extender reference serial control mode quellan , inc. = sma connector a) dc blocking capacitors = x7r or cog 0.1f (>4ghz bandwidth) impedance select (channels 3 and 4) impedance select (channels 1 and 2) d i do cp3[a] cp3[b] cp3[c] cp4[a] cp4[b] cp4[c] nc serial data in serial data out clk enb cp1[a] cp1[b] cp1[c] cp2[a] cp2[b] cp2[c] nc serial clock in enable active low mode at 1.2v: serial control mode mode at gnd: binary control mode 1.2v 100k 47nf 42.2k
fn6979 rev 2.00 page 22 of 23 june 23, 2016 qlx4600-s30 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordingly, the reader is cautioned to verify that datasheets are current before placing orders. information fu rnished by intersil is believed to be accu rate and reliable. however, no responsib ility is assumed by intersil or its subsidiaries for its use; nor for any infrin gements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html ? copyright intersil americas llc 2009-2016. all rights reserved. all trademarks and registered trademarks are the property of their respective owners. about intersil intersil corporation is a leading provider of innovative power ma nagement and precision analog so lutions. the company's product s address some of the largest markets within the industrial and infrastr ucture, mobile computing and high-end consumer markets. for the most updated datasheet, application notes, related docu mentation and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask . reliability reports are also av ailable from our website at www.intersil.com/support . revision history the revision history provided is for in formational purposes only and is believ ed to be accurate, but not warranted. please go to the web to make sure that you have the latest revision. date revision change june 23, 2016 fn6979.2 updated entire datasheet applying intersil?s new standards. updated the first paragraph on page 1 by adding ?displayport v1.2 (hbr1/2),?. updated applications bullet replaced qsfp with ?displayport v1.2? combined ?xaui and rxaui? and ?sas (1.0 and 2.0)? application bullets. added notes 1 and 3 to the ordering information table on page 2. added note 5 on page 5. removed symbol from maximum specification for ??high? resistance state? on page 5. added note 7 on page 7 and referenced in specification tables. updated figure 27 on page 13. added revision history and about intersil sections. updated pod l46.4x7 to the latest revision changes are as follows: -3/15/13 side view, changed pkg thickness from 0.70+/-0.05 to 0.75+/-0.05 detail x, changed from 0.152 ref to 0.203 ref.
qlx4600-s30 fn6979 rev 2.00 page 23 of 23 june 23, 2016 package outline drawing l46.4x7 46 lead thin quad flat no-lead plastic package (tqfn) rev 1, 3/13 located within the zone indicated. the pin #1 indentifier may b e unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but mus t be between 0.15mm and 0.30mm from the terminal tip. dimension applies to the metal lized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" side view typical recommended land pattern top view c 0.203 ref 0 . 05 max. 0 . 00 min. 5 4.00 a b 7.00 (4x) 0.05 6 pin 1 index area 39 46 2.80 42x 0.40 exp. dap 15 1 38 23 46x 0.40 16 6 5.60 ( 6.80 ) ( 5.50 ) ( 46 x 0.60) (46x 0.20) ( 42x 0.40) ( 3.80 ) ( 2.50) 2.50 0.1 0.10 46x 0.20 a mc b 4 5.50 0.1 exp. dap 0.75 0.05 see detail "x" seating plane 0.05 0.10 c c c 24 side view pin 1 index area

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